Key note address
The Magic of Flat Carbon
Dr. Kostya Novoselov
School of Physics & Astronomy
Graphene - the two-dimensional (2D) allotrope of carbon - possesses a number of unique properties. It is the first example of the truly 2D crystals - the very existence of which in a free state has been debated for a long time. It also demonstrates very unusual electronic properties - thanks to the linear spectra of quasiparticles. All these make graphene a unique material for a a number of applications: from composite materials to transparent conductive coating and high-frequency transistors.
Invited speakers
Interconnects Reliability
Dr. K. Croes
IMEC vzw,
Interconnect & Packaging department
During the talk, three of the main challenges a researcher in BEOL reliability needs to tackle during the downscaling of interconnect dimensions and the introduction of low-k materials will be covered. First, the need for performing low voltage dielectric breakdown measurements is discussed. After this, the main pitfalls when interpreting stress-induced-voiding data with copper VIA's integrated in low-k materials will be explained. Finally, the ways to adapt future finite element models to the current knowledge on stress dependence of interconnect pitches and dielectric porosity will be discussed. All three items will be illustrated with examples
Chalcogenide-based memories and materials
Dr. V. Sousa
CEA LETI MINATEC
In this talk, we will discuss the unique properties of chalcogenide glasses in relation to their atomic bonding structure, which make them suitable as base material for solid state memories. In particular, we will present their remarkable crystallization behaviour and electronic properties which are key properties for PCRAM memories. We will also discuss the super-ionic conduction of some chalcogenide glasses containing silver which is the basis of CBRAM memories.
Advanced Evaluation of CoWP Electroless Capping in an Manufacturing Context
for the 32 nm Technology Node and Beyond
Dr. Sebastien PETITDIDIER, Ph. D.
STMicroelectronics
CoWP electroless capping is now clearly foreseen as a process solution to enhance electromigration performance of Cu interconnects for 32 nm technology node and beyond. However, several concerns on robustness and stability of a new plating process step while exposing ultra-low k dielectric with 100 nm pitch can only be cleared by testing such a process in a manufacturing environment through significant volume. The purpose of this talk will be to review some of the challenge addressed by the introduction of CoWP in a manufacturing context detailing some of the key defectivity aspects and process adjustments needed to achieve compatibility with ultra-low k dielectric reliability without compromising the improvement in Cu lifetime.
Study of Intrinsic Low-k Properties Using a Novel Test Structure
Dr Larry Zhao
Intel Corp
A novel test structure based on a planar capacitor design has been used for investigation of intrinsic low-k properties. Low-k films with k value ranging from 3.2 to 2.2 have been studied for leakage current and time-dependent-dielectric-breakdown. In addition, this paper will also present low-k thickness scaling results, which can be used to understand the limits of future interconnect pitch scaling.
Embedded memory solutions and possible integrations
Dr Pascale Mazoyer
STMicroelectronics
Embedded memory solutions and possible integrations Convergence of consumer, computer and communication is leading to an exponential growth in complex electronic systems. Characteristics in terms of density, performance, power consumption, packaging and interfacing become of greater interest. If capabilities provided by the new memory technologies, concepts and materials proposed today drive the definition, solutions are developed regarding integration and compatibility with existing platforms.
Wireless interchip interconnects
Professor Kikkawa
Research Institute for Nanodevice and Bio Systems Graduate School of
Advanced Sciences of Matter Hiroshima University
1-4-2 Kagamiyama, Higashi-hiroshima, Hiroshima, Japan
In order to eliminate the RC delay of conventional metal interconnects, wireless interconnects have been developed for interchip link, stacked multi-chip packaging and three-dimensional integrated circuits. In this paper wireless interconnection technologies such as capacitance coupling, inductance coupling and transverse electromagnetic wave propagation are investigated for future interchip interconnects.
Nanowire growth and processing for wraped-gate FET
Dr Mikael Björk
Research Staff Member
IBM Research Zurich
Säumerstrasse 4 / Postfach
CH-8803 Rüschlikon
Switzerland
(Abstract not yet received)
Silicides
Dr C. Lavoie
Thin Film Metallurgy and Interconnections
IBM Research
1101 Kitchawan rd, Yorktown Heights, NY 10598
email: clavoie@us.ibm.com
(Abstract not yet received)
